1. Technical Field
The present invention relates to multi-layer substrates, and particularly to multi-layer substrates suitable for mounting of semiconductor devices such as integrated circuits.
2. Related Art
In the related art, multi-layer substrates having high degree of freedom with respect to wiring are used as a substrate for mounting semiconductor devices such as integrated circuits. Reference numeral 106 in FIG. 9A is a multi-layer substrate, and is made up of a plurality of laminated single layer substrates 101.
Each single layer substrate 101 comprises a base film 122 formed of a polyimide film, a wiring film 115 disposed on the base film 122, and an adhesive film 121 arranged on the wiring film 115 and the base film 122. Conductive bumps 116 are formed on the wiring film 115, and the tips of the bumps 116 project from the top of the adhesive film 121. The base film 122 is subjected to patterning a specified locations of a rear surface of the wiring film 115 are partially exposed.
When a plurality of the single layer substrates 101 are laminated on top of one another, bumps 116 of one single layer substrate 101 confront the rear surface of the wiring film 115 of a single layer substrate 101 laminated on top of it, tips of the bumps 116 are brought into contact with the rear surface of the wiring film 115, and they are then stuck together using the adhesive film 121, a multi-layer substrate 106 having a desired number of films is obtained.
The surface of this multi-layer substrate 106 is covered by a protective film 120, and bumps represented by reference numeral 116a project from the surface of the protective film 120.
Reference numeral 133 represents a semiconductor device, and has a plurality of circuits formed insides. This circuit is connected to bonding pads 134 formed on the semiconductor device 133. The bonding pads 134 confront the surface of the multi-layer substrate 106, the bonding pads 134 are made to contact the bumps 116a, as shown in FIG. 9B, thermo-compression bonding is carried out to melt a soldered film of the surface of the bumps 116a, and the circuits inside the semiconductor device 133 are connected to the wiring films 115 inside the multi-layer substrate 106 via the bonding pads 134 and the bumps 116a. When a semiconductor device 133 in chip form is mounted on a multi-layer substrate 106 described above, there is no need to package the semiconductor device 133, contributing significantly to miniaturization of an electronic device.
However, if the semiconductor device 133 is mounted on the multi-layer substrate 106 of the related art described above, the overall thickness of the multi-layer substrate 106 is disadvantageously increased by the thickness of the semiconductor device 133.
Also, with the multi-layer substrate 106 of the related art, since it is necessary to protect the semiconductor device 133, when the semiconductor device 133 is covered with resin 135, as shown in FIG. 9C, the overall thickness is further increased by the thickness of the resin 135.
In recent years, in the field of portable telephones and lap top and palm top personal computers, there has been a demand for further miniaturization and thinning of appliances, which has lead to the demand for multi-layer substrates to be thin even when semiconductor devices are mounted on them.
The present invention has been conceived in view of the above described problems in the related art, and the object of the present invention is to provide a multi-layer substrate that does not suffer increased thickness, even when semiconductors are mounted.
In order to solve the above described problems, a multi-layer substrate of the present invention comprises a plurality of at least first single layer substrates.
A first single layer substrate used in the present invention has a first resin film, a first wiring film arranged on the first resin film, and through holes passing through from a front surface to a rear surface.
In the present invention, at least two of the first single-layer substrates are electrically connected together, and the through holes are arranged so as to be aligned, forming a housing section.
Generally, the surface area of a semiconductor chip is 1 mm2 or more, which means that it is necessary for the surface area of each of the through holes to also be at least 1 mm2, and the surface area of opening of the housing section formed by laminating the through holes also becomes at least 1 mm2. The depth of the housing section is determined by the number of first single layer substrates laminated on top of one another.
Also, the first single layer substrate of the present invention has first bumps connected to the first wiring film and first connection holes formed on the first resin film, the first wiring film being located on the bottom surface of the first connection holes.
In another aspect of the present invention, of two adjacent first single layer substrates, first bumps of one first single layer substrate are connected to positions of the first wiring film at bottoms of the first connecting holes of the other first single layer substrate.
Accordingly, the multi-layer substrate of the present invention has desired first wiring films within laminated first single layer substrates electrically connected.
In another aspect of the multi-layer substrate of the present invention, a first adhesive film arranged on the first wiring film and exhibiting adhesiveness upon application of heat is provided on the first single layer substrates, and tips of the first bumps project from the surface of the first adhesive surface.
In this case, a plurality of the first single layer substrates are placed in adhered while heating, and the first single layer substrates are stuck together by the resultant adhesive force of the first adhesive layer.
In yet another aspect of the multi-layer substrate of the present invention also has a second single layer substrate.
In a still further aspect, the second single layer substrate comprises a second resin film, and a second wiring film arranged on the second resin film, with no through holes at least at positions where the housing section is formed.
This second single layer substrate is further laminated on the laminated first single layer substrates, and the second single layer substrate is located on the bottom surface of the housing section.
Further, another aspect of the multi-layer substrate of the present invention has the second wiring film of the second single layer substrate electrically connected to at least part of the first wiring film of the first single layer substrate adjacent to the second single layer substrate.
Also, the second single layer substrate of the multi-layer substrate of the present invention has second bumps connected to the second wiring film, the second bumps being connected to the first wiring film located in bottom sections of the first connection holes of the first single layer substrate adjacent to the second single layer substrate.
Also, the second single layer substrate of the multi-layer substrate of the present invention has second connection holes, arranged on the second resin film, the second wiring film being located on a bottom surface of the second connection holes, and first bumps of the first single layer substrate adjacent to the second single layer substrate are connected to positions of the second wiring film at the bottoms of the second connection holes.
A still further aspect of the second single layer substrate of the multi-layer substrate of the present invention has a second adhesive layer, arranged on the second wiring film, exhibiting adhesiveness upon application of heat, and tips of the second bumps project from a surface of the second adhesive film, the second single layer substrate laminated to the first single layer substrate by adhesive force of the second adhesive layer.
The multi-layer substrate of the present invention has the second bumps arranged on a bottom surface of the housing section.
On the other hand, the multi-layer substrate of the present invention has bonding pads formed on the second adhesive layer of the second single layer substrate using openings having the wiring film positioned on a lower surface, and the bonding pads are arranged on the bottom surface of the housing section.
It is possible to arrange one or both of the second bumps and the bonding pads on the bottom surface of the housing section.
With the multi-layer substrate of the present invention, the first bumps of the first single layer substrate are connected to the second wiring film positioned inside the second connection holes of the second single layer substrate, and the first single layer substrate and the second single layer substrate are stuck together using adhesive force of the first adhesive layer. The multi-layer substrate of the present invention has an electrical element disposed inside the housing section formed by the through holes of the laminated first single layer substrates.
The electrical element of the multi-layer substrate of the present invention is electrically connected to the second bumps arranged on the bottom surface of the housing section.
In the case where the electric element is a semiconductor device in a chip state, a metallic wiring film of the semiconductor device is connected to the second bumps.
On the other hand, inside another multi-layer substrate of the present invention, the electrical element Is connected to the bonding pads of the second single layer substrate arranged on the bottom surface of the housing section.
In this case, when the electric elements a semiconductor device in a chip state, bumps of the semiconductor device are connected to the bonding pads.
With the multi-layer substrate of the present invention, the housing section is covered by a covering single layer substrate having at least a resin film.
The multi-layer substrate of the present invention has a wiring film provided on the resin film of the covering single layer substrate. It is possible to laminate the first or second single layer substrates on the covering single layer substrate. It is also possible for the covering single layer substrate to use the second single layer substrate.
The multi-layer substrate of the present invention also has a wiring film of larger surface area than the semiconductor device arranged at positions of the housing section is likely to be elongated will hypothetically be elongated in the laminating direction that is, at positions of the housing section is likely to be elongated will hypothetically be elongated in the laminating direction that is. This large surface area wiring film can be connected to a ground potential and used as a shield layer.
The present invention has the above described structure, and is a multi-layer substrate that can house an electrical element such as s semiconductor integrated circuit inside a housing section formed using a multi-layer substrate, constructed by laminating single layer substrates, and a cavity inside the multi-layer substrate.
The multi-layer substrate of the present invention is formed by laminating a plurality of single layer substrates. For example, it is possible to construct the multi-layer substrate by forming an adhesive layer on respective single layer substrates and causing the adhesive layers to come into contact with resin films to connect each of the single layers to a substrate.
The first and second wiring films of the first and second single layer substrates of the present invention are defined on first and second resin films by patterning copper foil or aluminum foil etc.
It is possible to form first and second bumps on the first and second wiring films. If openings are then formed in the first and second resin films and the first and second wiring films exposed to form connecting sections at bottoms of the resin layers, then when the first single layer substrate and the second single layer substrate are laminated, bumps of one adjacent single layer substrate are aligned with connecting sections of the other adjacent single layer substrate, and tips of the bumps are connected to the wiring film at the bottoms of the connecting sections to electrically connect wiring films of the respective single layer substrates using the bumps.
A solder film is provided on the surface of the bumps, and if the solder is melted while bring the bumps into contact with the wiring film and fixing them together, the bumps are mechanically and electrically connected to the wiring film by the solder which means that the connection between laminated wiring films is reliable.
The first single layer substrates of the present invention have through holes, and if the through holes of a plurality of first single layer substrates are aligned and laminated, the housing section is formed by the aligned through holes. If the second single layer substrate is further laminated on the multi-layer substrate of laminated first single layer substrates, the second single layer substrate is located on the bottom surface of the housing section.
If the second bumps are caused to be exposed at sections of the second single layer substrate at the housing section bottom surface, then when an electrical element such as a semiconductor integrated circuit is housed Inside the housing section of the multi-layer substrate leads leading out from the electrical component and a metallic wiring film formed on the surface of the electrical element can be connected to the bumps.
An anisotropy conductive film is arranged between the bumps and the metallic wiring, and it Is possible to connect between the bumps and the metallic wiring or the leads using the adhesive force and electrical connectivity of the anisotropy conductive film, and it is also possible to connect the metallic wiring of the electrical element and the leads using solder on the surfaces of the bumps.
Further, by causing the second wiring film of the second single layer substrate to be exposed at the housing section bottom surface it is possible to bring the leads and bumps provided on the electrical element into contact with each other and connect them. In this case, it is preferable to form a solder film in advance on the surfaces of the electrical element leads and bumps and connect to the second wiring film using the solder, and it is also possible to use an anisotropy conductive film.
It is also possible to cover the electrical element using a single layer substrate or a multi-layer substrate of laminated single layer substrate, after housing the electrical element in the housing section and electrically connecting to the second wiring film of the second single layer substrate on the housing section bottom surface. The surface of the multi-layer substrate after covering becomes uniform.
The initial depth of the housing section housing the electrical element is shallower than the thickness of the electrical element, and it is also possible to form the housing section in a cover side single layer substrate using a first single layer substrate and to house an upper part of the electrical element inside the cover side housing section. It is possible to electrically connect first wiring films of first single layer substrates forming two housing sections.
If a wiring film having a larger surface area than the electrical element is provided on the multi-layer substrate and this wiring film is connected to a ground potential as a shield section, noise does not penetrate to the electrical element contained inside the housing section of the multi-layer substrate. It is possible to arrange the shield section on both the front and rear surfaces of the electrical element. In the event that the electrical element is a semiconductor integrated circuit, a surface of a semiconductor substrate inside the semiconductor integrated circuit opposite to a surface on which microscopic electrical elements are formed is grounded, so that it is possible to provide a shield section only on the surface where the microscopic electrical elements are formed.